This invention relates to the method of fabricating a semiconductor device, particularly to the method of fabricating a semiconductor device with a three-dimensional structure having a Metal Oxide Semiconductor (MOS) element.
The semiconductor devices in semiconductor integrated circuits usually consist of three layers having a Si substrate, a gate insulation layer and a gate electrode.
The insulation layers of these devices are usually formed of SiO.sub.2. Such SiO.sub.2 layers are often formed by thermally oxidizing the Si substrate or by using the Chemical Vapor Deposition (CVD) method. For electrical isolation among devices in a semiconductor integrated circuit a thick SiO.sub.2 layer is formed by the same method. This is desirable for minimizing stray (parastic) capacitance between the Si substrate and wirings of the surface part. However, the SiO.sub.2 layers, which are formed by thermal oxidation or by the CVD method, are usually noncrystalline.
Therefore, after such noncrystalline SiO.sub.2 layers are formed on the Si substrate, it is difficult for a single crystalline Si layer to be formed on the SiO.sub.2 layer. The polycrystalline Si which is employed will include many more grain boundary defects than single crystalline Si. Consequently the carrier mobility of the polycrystalline Si is 100 times smaller than that of single crystalline Si. There is also a phenomena that a doped impurity in the grain boundary will diffuse the other grains. The grain boundary size grows during the thermal step as disclosed, for example, in the laser anneal technology disclosed in the Japanese Journal of Applied Physics, Vol. 19, No. 1, Jan., 1980, pp. 23--26. It is difficult to reproduce electrical characteristics of the semiconductor device under such conditions. Therefore, the formation of a single crystalline Si layer on the insulation layer is important for the realization of the three-dimensional integrated circuits.